Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
| Autor: | Po-Yi Kuo, Jer-Yi Lin, Ko-Li Lin, Chun-Chieh Chin, Tien-Sheng Chao |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Fabrication Materials science business.industry Doping Transistor Nanowire Nanotechnology 02 engineering and technology Surface finish 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials law.invention Thin-film transistor law Etching (microfabrication) 0103 physical sciences Optoelectronics Trimming Electrical and Electronic Engineering 0210 nano-technology business |
| Zdroj: | IEEE Transactions on Electron Devices. 63:4998-5003 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2016.2615805 |
| Popis: | In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}) \sim 7 \times 10^{6}$ can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future. |
| Databáze: | OpenAIRE |
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