Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

Autor:	Ying-Hsi Lin, Tzu-Chi Huang, Chao-Cheng Lee, Tsung-Yen Tsai, Chao-Chang Chiu, Cheng-Chen Yang, Long-Der Chen, Chen-Chih Huang, Ke-Horng Chen, Shen-Yu Peng, Yu-Huei Lee
Rok vydání:	2013
Předmět:	Standard cell Power management Engineering Digital signal processor Switched-mode power supply business.industry Low-power electronics Electronic engineering System on a chip Electrical and Electronic Engineering business Instruction cycle Dynamic voltage scaling
Zdroj:	IEEE Journal of Solid-State Circuits. 48:2649-2661
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2013.2274885
Popis:	This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-μm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/μs saved 53% power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::8612a8f78733b06c138e0847d2639411 https://doi.org/10.1109/jssc.2013.2274885 Zobrazit plný text záznamu