Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

Autor:	K.-W. Lee, Kang-Wook Park, Won Ji Park, Young-Jin Wee, S. W. Nam, H. K. Kang, Kang-Deog Suh, Young-Joon Moon, I.G. Kim, Jae-Chul Kim, Seungmoo Lee, Hyun-Eok Shin, J.W. Hwang
Rok vydání:	2004
Předmět:	Materials science business.industry Copper interconnect Oxide Polishing Dielectric chemistry.chemical_compound chemistry Etching (microfabrication) Silicon carbide Electronic engineering Optoelectronics Node (circuits) business Lithography
Zdroj:	Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
DOI:	10.1109/iitc.2004.1345683
Popis:	A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::85f86d9fa2649cfe83611dd9446da0c3 https://doi.org/10.1109/iitc.2004.1345683 Zobrazit plný text záznamu