An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS
| Autor: | Kyoung-Jun Moon, Eun-Ji An, Dong-Ryeol Oh, Won-Mook Lim, Ye-Dam Kim, Seung-Tak Ryu |
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| Rok vydání: | 2021 |
| Předmět: |
Physics
Spurious-free dynamic range Dynamic range Amplifier 020208 electrical & electronic engineering 02 engineering and technology Flash ADC CMOS Effective resolution bandwidth Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Bandwidth (computing) Figure of merit Electrical and Electronic Engineering |
| Zdroj: | IEEE Journal of Solid-State Circuits. 56:1216-1226 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2020.3044624 |
| Popis: | An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 $\times $ interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step. |
| Databáze: | OpenAIRE |
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