IEEE Standard 1149.1 Test Access Port And Boundary Scan Implementation In High Density CMOS Gate Arrays

Autor:	Madhukar K. Reddy, R. Jones, Dandas Tang Dandas Tang
Rok vydání:	2005
Předmět:	Engineering Boundary scan business.industry Division (mathematics) Signal Reduction (complexity) CMOS Application-specific integrated circuit Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering business Hardware_LOGICDESIGN Communication channel
Zdroj:	Proceedings of the IEEE Custom Integrated Circuits Conference.
DOI:	10.1109/cicc.1992.591297
Popis:	This paper summarizes the implementation of IEEE 1149.1 test logic in Motorola ASIC Division's H4C SeriesTM of threelayer metal sub-micron (0.7 p effective channel length) CMOS gate arrays and advantages. The Boundary Scan Chain (BSC) logic and buffers for the BSC signals are implemented in the Periphery of gate arrays. This led to compact implementation of the BSC cells and interconnections, higher utilization of the core area for system logic, and reduction in delay in the system signal path through the BSC logic.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::85f40028f28d7cffedd69888f68e9b7a https://doi.org/10.1109/cicc.1992.591297 Zobrazit plný text záznamu