An integratable 1-2.5 Gbps low jitter CMOS transceiver with built in self test capability

Autor:	Ah-Lyan Yee, A. Tsong, V. Pathak, Martin J. Izzard, E. Suder, J.M. Tran, R. Prentice, R. Venett, S. Spencer, R. Gu, Heng-Chih-Lin
Rok vydání:	2003
Předmět:	Standard cell Phase-locked loop Engineering CMOS Application-specific integrated circuit business.industry Hardware_INTEGRATEDCIRCUITS Electronic engineering Transceiver business Phase detector Clock recovery Jitter
Zdroj:	1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
DOI:	10.1109/vlsic.1999.797230
Popis:	This paper describes a high speed, low jitter CMOS transceiver, which includes 10 to 1 full duplex serialize-deserialize function, clock recovery, high speed differential I/O, and Built In Self Test (BIST). It was fabricated and tested to work at wide frequency range (1 to 2.5 Gbps) with low jitter and low power (76 ps P-P, 500 mW @ 2.5 Gbps). It was designed to be a component of ASIC standard cell library and was implemented as a stand alone design as well as in a large design with 32 transceivers.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::85947ad9fa86945340e03474262ce97d https://doi.org/10.1109/vlsic.1999.797230 Zobrazit plný text záznamu