Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs
| Autor: | Yongfeng Cao, Xiuhao Zhang, Zewei Wang, Jialun Li, Lingge Liu, Xin Luo, Yumeng Yuan, Shoumian Chen, Zhidong Tang, Xufeng Kou, Qiming Shao, Chengwei Cao, Ao Guo, Shaojian Hu, Yuhang Zhao |
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| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Materials science Semiconductor device modeling Geometry Hardware_PERFORMANCEANDRELIABILITY 01 natural sciences Electronic Optical and Magnetic Materials PMOS logic Computer Science::Hardware Architecture Computer Science::Emerging Technologies CMOS Depletion region Logic gate 0103 physical sciences MOSFET Hardware_INTEGRATEDCIRCUITS BSIM Electrical and Electronic Engineering NMOS logic Hardware_LOGICDESIGN |
| Zdroj: | IEEE Electron Device Letters. 41:661-664 |
| ISSN: | 1558-0563 0741-3106 |
| DOI: | 10.1109/led.2020.2984280 |
| Popis: | This paper presents experimental characterizations and device modeling on the nanoscale MOSFETs with 40 nm low-power CMOS technology. Systematic temperature-dependent ${I}_{D}$ - ${V}_{GS}$ results of NMOS/PMOS devices reveal that both the threshold voltage and the effective channel mobility exhibit strong correlations with the device size owning to the depletion region broadening around the gate channel at cryogenic temperatures. By taking the temperature-driven gate geometry effects into consideration, a generic physical model with universal fitting parameters is proposed to depict the transfer characteristics of all CMOS transistors across the device size chart, and further validations of the modified BSIM compact model might pave the way for an accurate design of cryogenic electronics applications. |
| Databáze: | OpenAIRE |
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