Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs
| Autor: | Lukas Sommer, Kristian Kersting, Julian Oppermann, Alejandro Molina, Andreas Koch, Lukas Weber |
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| Rok vydání: | 2019 |
| Předmět: |
Floating point
Artificial neural network Logarithm Computer science Logarithmic number system Inference 02 engineering and technology 020202 computer hardware & architecture Computer Science::Hardware Architecture 0202 electrical engineering electronic engineering information engineering Range (statistics) 020201 artificial intelligence & image processing Graphical model Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Field-programmable gate array |
| Zdroj: | FPT |
| DOI: | 10.1109/icfpt47387.2019.00040 |
| Popis: | FPGAs have been successfully used for the implementation of dedicated accelerators for a wide range of machine learning problems. The inference in so-called Sum-Product Networks can also be accelerated efficiently using a pipelined FPGA architecture. However, as Sum-Product Networks compute exact probability values, the required arithmetic precision poses different challenges than those encountered with Neural Networks. In previous work, this precision was maintained by using double-precision floating-point number formats, which are expensive to implement in FPGAs. In this work, we propose the use of a logarithmic number system format tailored specifically towards the inference in Sum-Product Networks. The evaluation of our optimized arithmetic hardware operators shows that the use of logarithmic number formats allows to save up to 50% hardware resources compared to double-precision floating point, while maintaining sufficient precision for SPN inference at almost identical performance. |
| Databáze: | OpenAIRE |
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