A 10b 1MS/s 0.5mW SAR ADC with double sampling technique

Autor:	Tagjong Lee, Phi-Hung Pham, Moo-Young Kim, Yongtae Kim
Rok vydání:	2009
Předmět:	Engineering Spurious-free dynamic range business.industry Successive approximation ADC computer.file_format Converters Power (physics) Data conversion law.invention Capacitor CMOS law Logic gate Electronic engineering business computer
Zdroj:	2009 International SoC Design Conference (ISOCC).
DOI:	10.1109/socdc.2009.5423831
Popis:	This paper introduces the 10b 1MS/s 0.5mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.111um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB, respectively at input frequency of 484kHz. Power consumption of the data converter is total 507uW with 1.2-V supply.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::845f2b9abb4a201b0355c612c9b02c55 https://doi.org/10.1109/socdc.2009.5423831 Zobrazit plný text záznamu