Ranking process parameter association with low yield wafers using spec-out event network analysis
| Autor: | Jiwon Yang, Young-Hak Lee, Seung-Kyung Lee, Seokho Kang, Sungzoon Cho, Hae-Sang Park |
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| Rok vydání: | 2017 |
| Předmět: |
0209 industrial biotechnology
Engineering General Computer Science Event (computing) business.industry Semiconductor device fabrication General Engineering Process (computing) 02 engineering and technology Process variable Directed graph computer.software_genre 020901 industrial engineering & automation 0202 electrical engineering electronic engineering information engineering Graph (abstract data type) 020201 artificial intelligence & image processing Node (circuits) Data mining business computer Network analysis |
| Zdroj: | Computers & Industrial Engineering. 113:419-424 |
| ISSN: | 0360-8352 |
| DOI: | 10.1016/j.cie.2017.09.036 |
| Popis: | In the semiconductor process, the time-series process sensor data such as temperature, pressure, and voltage, are analyzed, to find suspicious process parameters associated with low yield wafers. A common approach is to compute correlation between individual spec-out events and defect ratios. However, the downside with this approach is that it ignores interactions among spec-out events, leading to each spec-out event being independently administrated. In this paper, we propose a novel approach that incorporates the interactions among spec-out events using spec-out event network analysis. We construct a weighted directed graph in which a spec-out event is represented as a node, a precedence relation between events as a directed edge, and the wafer defect ratio corresponding to the relation as an edge weight. In this graph, a more important node in the process will have more links from other succeeding nodes with high defect ratios. The PageRank algorithm run on this event network results in a ranking of association with wafer defects. We validated the performance using real-production data from a 32 nm device. The proposed method enables process engineers to determine the root causes of low yield wafers due to the interactions of the process steps. |
| Databáze: | OpenAIRE |
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