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In recent technology nodes, interconnect scaling has become a major bottleneck for the reduction of the area of CMOS circuits. In the near future, interconnect dimensions will reach 10 nm and below. Reducing the cross-sectional area of interconnect wires and vias increases their resistance and consequently degrades the performance of the circuit. This geometrical effect is aggravated by an increased resistivity of the conductor metal, Cu, due to enhanced surface and grain boundary scattering. Moreover, it becomes increasingly difficult to ensure the reliability of scaled Cu interconnects. Barrier layers, such as TaN, are required to limit diffusion into the surrounding dielectrics. Resistance to electromigration is reduced in small dimensions, which can be mitigated e.g. by Co liners. However, both barriers and liners reduce the volume available for Cu while contributing little to the line conductance. These issues have recently led to an increased research for alternatives to the current Cu dual damascene interconnect technology. Materials innovation is a key to mitigate the reduction of interconnect performance. An ideal conductor metal allows for reliable interconnect operation without requiring barrier or liner layers, thus maximizing the available conductor volume. Moreover, it possesses a lower sensitivity to surface and grain boundary scattering than Cu, which means that the resistivity degrades more gradually with reduced interconnect line width. This property can be linked to a smaller mean free path of the charge carriers with respect to Cu (~40 nm) and thus metals with short mean free paths have been of particular interest. To identify suitable alternative conductor metals, we have developed a staged approach, which is schematically represented in the figure. Ab initio calculations of the product of the bulk resistivity and the mean free path as a figure of merit [1,2] are used to shortlist potential candidate metals. While a short mean free path indicates a weak sensitivity to finite size effects of the resistivity due to enhanced surface and grain boundary scattering, a low bulk resistivity is of equal importance to ensure a low resistivity at small dimension. By contrast, the cohesive energy (or the melting point) of a metal can be used as proxies for its expected electromigration performance and the need for barrier layers. This approach has now been applied to all relevant elemental metals as well as many binary and some ternary intermetallics. As concerns elemental metals, Co, Mo, as well as the Pt-group metals show particularly promising behavior. We will also review the situation for binary and ternary intermetallics. In a next step, thin film experiments have been used to assess the performance of the shortlisted metals experimentally. We will show that in particular several Pt-group metals show lower resistivities than Cu for ultrathin films with thicknesses below 10 nm. In addition, opportunities and challenges of binary or ternary intermetallics with respect to elemental metals will be discussed. In a third step, scaled interconnect wires of different alternative metals have been fabricated using a metal spacer process based on ion-beam etching [3-5]. The results indicate that Co, Ru, Ir, and Rh show promise to outperform Cu in narrow dimensions. Calibrated compact models of the line resistance indicate that the main gain in resistance over Cu interconnect lines and vias stems from the increased conductor volume since no barrier and line layers are required for reliable operation with a smaller contribution of the reduced resistivity. Finally, the remaining challenges in the integration of alternative metals in scaled interconnects are discussed. [1] D. Gall, J. Appl. Phys. 119, 085101 (2016). [2] S. Dutta, K. Sankaran, K. Moors, G. Pourtois, S. Van Elshocht, J. Bömmels, W. Vandervorst, Z. Tőkei, and C. Adelmann, J. Appl. Phys. 122, 025107 (2017). [3] L.G. Wen, et al., ACS Appl. Mater. Interfaces 8, 26119 (2016). [4] S. Dutta, S. Kundu, A. Gupta, G. Jamieson, J.F. Gomez Granados, J. Bömmels, C.J. Wilson, Z. Tőkei, and C. Adelmann, IEEE Electron Dev. Lett. 38, 949 (2017). Figure 1 |
