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With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology. Fan-out WLP is one of key advanced packages because of advantages of higher number of I/Os, process easiness and integration flexibilities. Furthermore, it enables to integrate mUltiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. This paper reports developments of next generation Fanout WLP for advanced packaging solutions .. A new portfolio of next generation package configurations: small outline Fanout WLP, double-side 3D Fan-out WLP and eWLL (embedded Wafer Level Land Grid Array) are developed and characterized. And the reliability study was carried out in depth by experimental approaches. Successful reliability characterization results on different package configurations are reported that demonstrate next generation Fan-out WLP as an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions. |
