| Autor: |
P. Coudrain, Sébastien Mermoz, C. Fretigny, L. Di Cioccio, L. Sanchez, E. Deloffre, Jean Berthier |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013). |
| DOI: |
10.1109/eptc.2013.6745705 |
| Popis: |
We present here our latest results on chips-to-wafer 3D structures obtained with the self-assembly technology adapted on copper/oxide patterned surfaces. Technological integration, bonding quality and alignment accuracy are presented and the electrical contact of the interconnection is evaluated. High speed high alignment accuracy chip-to-wafer hybridation technique is mandatory for 3D technology. Chip-to-wafer self-assembly processes coupled to direct bonding hybridization is on the merge to breakthrough this issue. In a previous work [1], we demonstrated submicronic alignment accuracy and a 90% self-assembly process yield with this technique. In this paper, we discuss on interconnect electrical characterization of self-assembled chips compared to chips assembled with conventional Pick and Place method. Interface resistance is evaluated on daisy chain and Kelvin structures. The quantification of the alignment is measured thanks to vernier and is in the range of a few hundred nanometers. The liquid drop impact on assembled structure, considering the different aspects (bonding quality, Cu-chemical oxidation, mechanical chip level bow and electrical resistance) is discussed. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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