Novel RDL Design of Wafer-Level Packaging for Signal/Power Integrity in LPDDR4 Application
| Autor: | Tsung-Yi Kuo, Ming-Tzong Yang, Kai-Bin Wu, I-Hsuan Peng, Ruey-Beei Wu, Cheng-Chou Hung, Benson Lin |
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| Rok vydání: | 2018 |
| Předmět: |
Computer science
020208 electrical & electronic engineering 020206 networking & telecommunications Power integrity 02 engineering and technology Decoupling capacitor Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials Power (physics) 0202 electrical engineering electronic engineering information engineering Electronic engineering RLC circuit Redistribution layer Signal integrity Electrical and Electronic Engineering Double data rate Wafer-level packaging |
| Zdroj: | IEEE Transactions on Components, Packaging and Manufacturing Technology. 8:1431-1439 |
| ISSN: | 2156-3985 2156-3950 |
| DOI: | 10.1109/tcpmt.2018.2850528 |
| Popis: | The emerging wafer-level packaging (WLP) technology suffers from serious signal integrity (SI) and power integrity (PI) issues due to its redistribution layer (RDL). There exhibit serious parasitic effects by the high-density RDL traces and less flexibility of decoupling capacitors, so the robust power distribution network is critical to design. This paper proposed a novel two-layered RDL design in low-power double data rate fourth generation (LPDDR4) application by proposing a novel power/ground meshed layout for superior PI performance. Besides, the second-order RLC simplified model and normalized resistance are derived to handle the process scaling issue for successful SI by adjusting the cross-sectional structure of RDL so that LPDDR4 4266 can work well on 2- $\mu \text{m}$ WLP. |
| Databáze: | OpenAIRE |
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