A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K
Autor: | Jun Okamoto, Koyo Nitta, Hiroe Iwasaki, Mitsuo Ikeda, Ken Nakamura, Naoki Ono, Takayuki Onishi, Kazuya Yokohari, Kimiko Kawashima, Takashi Sano, Atsushi Shimizu, Yukikuni Nishida, Atsushi Sagata |
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Rok vydání: | 2018 |
Předmět: |
business.industry
Computer science 02 engineering and technology Chip Motion vector 020202 computer hardware & architecture Hardware and Architecture Motion estimation Histogram Bit rate Scalability 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Electrical and Electronic Engineering business Encoder Software Computer hardware |
Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:1930-1938 |
ISSN: | 1557-9999 1063-8210 |
Popis: | A professional-image-quality video encoder LSI for broadcasting and content distribution has been developed with single-chip 4K 60-fps 4:2:2 high-efficiency video coding (HEVC) encoding capability and 8K ultrahigh definition television scalability. Edge-based intramode pruning and statistically adaptive multiblock-size motion estimation (ME) efficiently reduce HEVC’s high computational complexity for real-time processing, while a deeply centralized-mode decision framework maintains high compression performance. Internal reference image caches with 797-Gb/s image feed capability support the 768-GOPS ME computation of distributed motion vector search. Interchip pictures and data exchange features with high-speed data buses are also used for multichip 8K encoding configuration. A subjective evaluation showed that the proposed encoder LSI maintained the same visual quality as an encoder LSI complying with the previous standard while reducing bit rate by 40%. The chip was designed and fabricated in a 28-nm CMOS technology and used to build industry-leading 4K and 8K broadcasting systems. |
Databáze: | OpenAIRE |
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