Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions
| Autor: | Tedi Kujofsa, John E. Ayers |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Threading dislocations Materials science Solid-state physics Condensed matter physics business.industry 02 engineering and technology 021001 nanoscience & nanotechnology Condensed Matter Physics 01 natural sciences Quantitative model Electronic Optical and Magnetic Materials Lattice mismatch Semiconductor Getter 0103 physical sciences Materials Chemistry Electrical and Electronic Engineering Dislocation 0210 nano-technology business |
| Zdroj: | Journal of Electronic Materials. 49:6977-6982 |
| ISSN: | 1543-186X 0361-5235 |
| Popis: | It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnSySe1-y/GaAs (001) relative to ZnSe/GaAs (001). |
| Databáze: | OpenAIRE |
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