500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

Autor: T. Furuyuma, Victor E. Lee, Kiyofumi Sakurai, Satoru Takase, Natsuki Kushiyama, Mark Horowitz, James A. Gasbarro, Wingyu Leung, D. Stark, Shigeo Ohshima, Matthew Murdy Griffin, Winston South San Francisco Lee, B. Barth, John B. Dillon
Rok vydání: 2003
Předmět:
Zdroj: 1992 Symposium on VLSI Circuits Digest of Technical Papers.
Popis: A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package. >
Databáze: OpenAIRE