3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture
| Autor: | Byung-Gook Park, Jong Duk Lee, Jang-Gn Yun |
|---|---|
| Rok vydání: | 2011 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES Fabrication business.industry Nand flash memory Process (computing) Condensed Matter Physics Electronic Optical and Magnetic Materials Interference (communication) Stack (abstract data type) Materials Chemistry Electronic engineering Optoelectronics Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Connection (algebraic framework) business Communication channel |
| Zdroj: | Solid-State Electronics. 55:37-43 |
| ISSN: | 0038-1101 |
| DOI: | 10.1016/j.sse.2010.07.019 |
| Popis: | A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|
Full Text from ScienceDirect