ILD0 CMP: Technology enabler for high K metal gate in high performance logic devices

Autor:	Garlen C. Leung, Christopher Heung-Gyun Lee, Sean Cui, Thomas H. Osterheld, Balaji Chandrasekaran, Lakshmanan Karuppiah, Anand N. Iyer, Jie Diao, Jun Qian
Rok vydání:	2010
Předmět:	Engineering Moore's law business.industry media_common.quotation_subject Die (integrated circuit) Logic gate Chemical-mechanical planarization Electronic engineering Optoelectronics Process control Wafer business Metal gate High-κ dielectric media_common
Zdroj:	2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
DOI:	10.1109/asmc.2010.5551458
Popis:	The extension of Moore's Law at the 45/32nm nodes is made possible by the introduction of high-k metal gate. In the gate-last scheme to integrate high-k metal gate, planarization and surface topography control have been reported as some of the biggest process challenges. This paper presents a three-platen chemical mechanical planarization process in which fixed abrasive is used on platen 2 and a non-selective slurry is used on platen 3 with a FullVision™ in-situ endpoint system. Superior planarization and dishing performance by the fixed abrasive and consistent endpoint control by FullVision enabled tight control of within wafer, within die and wafer-to-wafer thickness variations that is critical to the success of high k metal gate in high performance logic devices.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::8216c01421a5792b8a11c43859c2081d https://doi.org/10.1109/asmc.2010.5551458 Zobrazit plný text záznamu