| Autor: |
Abde Kaqalwalla, Nuo Xu, Lynn T.-N. Wang, Puneet Gupta, Costas J. Spanos, Tiehui Liu, Tuck-Boon Chan, Kwangok Jeong, Kameshwar Poolla, Kenji Yamazoe, Anand Subramanian, Xin Sun, Justin Ghan, Marshal A. Miller, Andrew R. Neureuther, Kun Qian, Eric Y. Chin, Cooper S. Levy, Rani S. Ghaida, Juliet Rubinstein |
| Rok vydání: |
2011 |
| Předmět: |
|
| Zdroj: |
SPIE Proceedings. |
| ISSN: |
0277-786X |
| DOI: |
10.1117/12.899394 |
| Popis: |
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits are described. These results are from multi-discipline, collaborative university-industry research and emphasize anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes design and testing electronic monitors in silicon at 45 nm and fast-CAD tools to identify systematic variations for entire chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow characterization. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
|
