A low power dynamic logic with nMOS based resistive keeper circuit
| Autor: | Riazul Islam, Kazi Fatima Sharif, Satyendra N. Biswas, Sunil R. Das, Mansour H. Assaf, Mahbubul Haque, Emil M. Petriu |
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| Rok vydání: | 2017 |
| Předmět: |
Pass transistor logic
Computer science business.industry Electrical engineering Logic family Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Circuit extraction 020202 computer hardware & architecture Logic gate Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering business Dynamic logic (digital electronics) NMOS logic Hardware_LOGICDESIGN Asynchronous circuit Logic optimization |
| Zdroj: | 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA). |
| DOI: | 10.1109/icimia.2017.7975597 |
| Popis: | Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation results using LTSpice tools demonstrate the validity and superiority of the proposed circuit. |
| Databáze: | OpenAIRE |
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