A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM
| Autor: | Koji Yanagida, Yohei Umeki, Koji Tsunoda, Hiroshi Kawaguchi, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Toshihiro Sugii |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Magnetoresistive random-access memory Bit cell Computer science Spin-transfer torque 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Computer Science Applications Process variation Non-volatile memory Tunnel magnetoresistance 0103 physical sciences Electronic engineering Static random-access memory Electrical and Electronic Engineering 0210 nano-technology Low voltage |
| Zdroj: | IPSJ Transactions on System LSI Design Methodology. 9:79-83 |
| ISSN: | 1882-6687 |
| DOI: | 10.2197/ipsjtsldm.9.79 |
| Popis: | The capacity of embedded memory on LSIs has kept increasing. It is important to reduce the leakage power of embedded memory for low-power LSIs. In fact, the ITRS predicts that the leakage power in embedded memory will account for 40% of all power consumption by 2024 [1]. A spin transfer torque magneto-resistance random access memory (STT-MRAM) is promising for use as non-volatile memory to reduce the leakage power. It is useful because it can function at low voltages and has a lifetime of over 1016 write cycles [2]. In addition, the STT-MRAM technology has a smaller bit cell than an SRAM. Making the STT-MRAM is suitable for use in high-density products [3–7]. The STT-MRAM uses magnetic tunnel junction (MTJ). The MTJ has two states: a parallel state and an anti-parallel state. These states mean that the magnetization direction of the MTJ’s layers are the same or different. The directions pair determines the MTJ’s magneto- resistance value. The states of MTJ can be changed by the current flowing. The MTJ resistance becomes low in the parallel state and high in the anti-parallel state. The MTJ potentially operates at less than 0.4 V [8]. In other hands, it is difficult to design peripheral circuitry for an STT-MRAM array at such a low voltage. In this paper, we propose a counter-based read circuit that functions at 0.4 V, which is tolerant of process variation and temperature fluctuation. |
| Databáze: | OpenAIRE |
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