Approaches to extra low voltage DRAM operation by SOI-DRAM
| Autor: | Hiroki Shimano, T. Nishimura, K. Shimomura, M. Inuishi, T. Oashi, S. Komori, F. Morishita, Takahisa Eimori, F. Okuda, H. Miyoshi, T. Iwamatsu, Yutaro Yamaguchi, Y. Inoue, Kazutami Arimoto, Narumi Sakashita |
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| Rok vydání: | 1998 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES business.industry Electrical engineering Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Capacitance Electronic Optical and Magnetic Materials law.invention Capacitor law Hardware_INTEGRATEDCIRCUITS Extra-low voltage Electrical and Electronic Engineering business Low voltage Dram Electronic circuit Voltage |
| Zdroj: | IEEE Transactions on Electron Devices. 45:1000-1009 |
| ISSN: | 0018-9383 |
| Popis: | The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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