A 20 ns 64K (4Kx16) NMOS RAM
| Autor: | P.E. Britton, V. Di Lonardo, B. Chappell, Stanley E. Schuster |
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| Rok vydání: | 1984 |
| Předmět: | |
| Zdroj: | IEEE Journal of Solid-State Circuits. 19:564-571 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.1984.1052190 |
| Popis: | A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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