| Autor: |
Chang-Yong Um, Yoon-Jong Song, F. Yeung, Jae-joon Oh, J.H. Kong, Gitae Jeong, Dae-Won Ha, Woon Ik Park, Junha Lee, J. H. Kim, Y.J. Jeon, Mi-Hyang Lee, D-H. Kang, J.H. Park, H.S. Jeong, J. Yu |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
2008 Symposium on VLSI Technology. |
| DOI: |
10.1109/vlsit.2008.4588577 |
| Popis: |
This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are: 1) the write-and-verify (WAV) writing of four-level resistance states; and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90 nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 108 cycles, respectively. In addition, they are non-destructively readable above 107 read pulses at 100 ns and 1 uA. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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