Scalability and Design-Space Analysis of a 1T-1MTJ Memory Cell for STT-RAMs
| Autor: | Dejan Markovic, Chih-Kong Ken Yang, Yuta Toriyama, Fengbo Ren, Richard Dorrance, Amr Amin Hafez |
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| Rok vydání: | 2012 |
| Předmět: |
Engineering
Hardware_MEMORYSTRUCTURES business.industry Transistor Design flow Integrated circuit design Electronic Optical and Magnetic Materials law.invention CMOS law Memory cell Scalability Electronic engineering Sensitivity (control systems) Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business Random access |
| Zdroj: | IEEE Transactions on Electron Devices. 59:878-887 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2011.2182053 |
| Popis: | We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ's critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( |
| Databáze: | OpenAIRE |
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