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Video is ever increasingly stimulating in electronics and multimedia applications such as video - telephony, video conferencing and video streaming to mobile phones via internet, in order to use effectively, the video is often compressed for low memory and fast transfer of video and then decompressed for use, so currently video compression a very active research topic, the compression is achieved through good Motion Estimation (ME). Motion Estimation is the power hungry block in the Video Compression System (VCS). The motion estimation operation determines the motion vectors, giving the best direction of the motion, and the "fitness" of that motion vector. The most widely used method to determine motion vectors is the Sum of Absolute Difference (SAD). In this paper we implemented the existing and the proposed 8×8 sum of absolute differences. Here the new low power full adder cell for low power applications is identified and is used in the proposed sum of absolute difference algorithm, the designs are implemented using ASIC flow, which results in 28.74% improvement in Leakage Power (LP) 12.201% improvement in Dynamic Power (DP) and 13.143% improvement in the total power even though the no of cells increased from 3933 to 4501. |
