VERILOG_A IMPLEMENTATION OF NANOWIRE JUNCTIONLESS ISFET COMPACT MODEL AND READ-OUT CIRCUIT DESIGN

Autor:	N.D. YEZAKYAN, A.E. YESAYAN, J-M. SALLESE
Rok vydání:	2022
Předmět:	Cancer Research Nutrition and Dietetics General Veterinary Oncology Endocrinology Diabetes and Metabolism Internal Medicine Medicine (miscellaneous) General Medicine Geriatrics and Gerontology Pediatrics Gerontology General Nursing Food Science
Zdroj:	Proceedings.
DOI:	10.53297/0002306x-2022.v75.3-398
Popis:	In this paper, we implement nanowire (NW) junctionless (JL) ISFET model in Verilog-A hardware language. The Verilog-A implementation would allow the NW ISFET integration with signal processing circuits. The simulated by the code pH values are compared with the corresponding data from COMSOL simulations, and a good agreement is observed. The readout circuit based on amperometric switched- capacitors schemes is designed. The readout circuit has introduced good linearity in pH values range from 3 to 7.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::80d9b628cbadca3a2ff28be7ebc86ae5 https://doi.org/10.53297/0002306x-2022.v75.3-398 Zobrazit plný text záznamu