A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
| Autor: | D.J. Schepis, F. Assaderaghi, D.S. Yee, W. Rausch, R.J. Bolam, A.C. Ajmera, E. Leobandung, S.B. Kulkarni, R. Flaker, D. Sadana, H.J. Hovel, T. Kebede, C. Schiller, S. Wu, L.F. Wagner, M.J. Saccamango, S. Ratanaphanyarat, J.B. Kuang, M.C. Hsieh, K.A. Tallman, R.M. Martino, D. Fitzpatrick, D.A. Badami, M. Hakey, S.F. Chu, B. Davari, G.G. Shahidi |
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| Rok vydání: | 2002 |
| Předmět: |
Physics
Interconnection Hardware_MEMORYSTRUCTURES business.industry Electrical engineering Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention Reliability (semiconductor) Integrated injection logic CMOS law Hardware_INTEGRATEDCIRCUITS Static random-access memory business Hardware_LOGICDESIGN Voltage |
| Zdroj: | International Electron Devices Meeting. IEDM Technical Digest. |
| DOI: | 10.1109/iedm.1997.650453 |
| Popis: | In this paper a 0.25 /spl mu/m SOI CMOS technology is described. It uses undepleted SOI devices with nominal channel length of 0.15 /spl mu/m, minimum channel length in the 0.1 /spl mu/m range, supply voltage of 1.8 V, local interconnect, 6 levels of metal, and same ground rules as the comparable bulk 0.25 /spl mu/m CMOS. Key technology elements considered include device, performance, reliability, ESD, and circuit functionality. Using this SOI CMOS, a 4 Mb SRAM is demonstrated. This is the highest performance 0.25 /spl mu/m CMOS technology reported to date. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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