Approximate Arithmetic Circuit Design Using a Fast and Scalable Method
Autor: | Amir Masoud Gharehbaghi, Masahiro Fujita, Qi Lu |
---|---|
Rok vydání: | 2019 |
Předmět: |
Adder
Artificial neural network Computer science Computation Circuit design Approximation algorithm 02 engineering and technology 020202 computer hardware & architecture Logic gate Scalability 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Arithmetic Electronic circuit |
Zdroj: | VLSI-SoC |
DOI: | 10.1109/vlsi-soc.2019.8920365 |
Popis: | Approximate computing can be applied to error-tolerant applications, by trading off accuracy for lower power consumption, shorter delay and smaller area. In this paper, we focus on the approximate arithmetic circuit design especially targeting combinational multipliers and adders, which are essential computing components in machine learning such as neural network computation. We propose a novel approach to generate approximate circuits from the given correct circuits. The basic idea is to study the circuit’s characteristics from the small instances of the circuits and then establish a common algorithm for larger circuits with the same architectures. We propose two different methods and apply them to adders and multipliers with different architectures. The experimental results demonstrate that our method outperforms the state-of-art methods in terms of the quality of the circuits with orders of magnitude shorter processing time. |
Databáze: | OpenAIRE |
Externí odkaz: |