Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements

Autor:	M. Rona, G. Krampl, H. Tauber
Rok vydání:	2003
Předmět:	Virtual instrumentation Computer science business.industry media_common.quotation_subject Hardware description language Test harness Automatic test equipment Software Debugging Embedded system VHDL business computer computer.programming_language media_common Test data
Zdroj:	ITC
DOI:	10.1109/test.2002.1041841
Popis:	Virtual test (VT) allows the debug of mixed-signal test programs and associated test hardware in a simulation environment if (1) a cheap, fast and sufficiently accurate chip model, and (2) a converter software linking test programs to simulators can be made available. This paper presents TSS (test setup simulation), a high-performance VT solution based on pure VHDL modeling of the hardware involved, a VHDL-based virtual tester concept and a snapshot test data extractor linking the test program to a simulator together with VT results for a complex telecom device.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::80248afff8ffbb1ab0d7f0b5e929fdd5 https://doi.org/10.1109/test.2002.1041841 Zobrazit plný text záznamu