Design and realization camera controller for a Remote Sensing Payload of nanosatellite FPGA (Field Programmable Gate Array) system based
| Autor: | Dwi Cahyono, Arifin Nugroho |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Engineering
business.product_category business.industry Payload law.invention Microprocessor Application-specific integrated circuit law Embedded system VHDL Ground segment business Field-programmable gate array computer Computer hardware computer.programming_language Remote sensing Digital camera ModelSim |
| Zdroj: | 2013 6th International Conference on Recent Advances in Space Technologies (RAST). |
| DOI: | 10.1109/rast.2013.6581306 |
| Popis: | Currently, satellite technology has been getting development in miniaturizing dimension and components to the level of 1 kg weight. Currently Institut Teknologi Telkom is developing nanosatellites for research purposes. Nanosatellite is one of a class of small satellites weighing less than 10 kg. Remote Sensing Payload is one of the subsystems that exist in nanosatellite. Payload subsystem serves to give an image that can be processed for purposes such as ship monitoring and tracking, border monitoring, deforestation and so on. One of the subsystems within the component nanosatellite is Camera Control or On-Board Data Handling (OBDH) remote sensing payload. The presence OBDH the payload subsystem platform nanosatellite to serve the processing of data from cameras, camera control, error correction, and raw data delivery to the transmitter.FPGA (Field Programmable Gate Arrays) are able to perform its function as OBDH. FPGA-based Camera Controller that in this research is designed to set the process and control bits data input from the camera to the SDRAM and output from the SDRAM to be sent to the Ground Segment (PC). Components are required as input the output information in the form of camera payload TCM8240MD, internal SDRAM FPGA board. Communication used between the camera and FPGA with I2C bus protocol (Inter-IC) bus protocol. This FPGA will be encoded in VHDL language. Software used in a VHDL design is WebPack XILINX ISE, ModelSim, XSTOOLs Utilities. The execution and realization will be conducted in the supporters laboratory such as Digital Techniques and Microprocessor and Interfacing Laboratory. FPGA used is a Xilinx Spartan-200A XuLA with a maximum operating frequency of 384 MHz because of its small dimension and low power consumption, and digital camera 1.3 Megapixels TCM 8240MD with the Camera Controller dimension is 7.5 x 8.4 × 2.5 cm an3 and the power is 513.178 mWatt and the mass total is 51.75 gram. Going forward, the algorithm is programmed with VHDL language will be generated into the ASIC to strengthen and make it solid logic gates in the VHDL language in future space technology. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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