100GB/S two-iteration concatenated BCH decoder architecture for optical communications
| Autor: | Ki Hoon Lee, Jeong-In Park, Han-Gil Kang, Hanho Lee |
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| Rok vydání: | 2010 |
| Předmět: |
Theoretical computer science
Interleaving Computer science business.industry Concatenated error correction code Concatenation Data_CODINGANDINFORMATIONTHEORY Coding gain Soft-decision decoder Viterbi decoder Bit error rate Forward error correction Error detection and correction business BCH code Decoding methods Computer hardware |
| Zdroj: | 2010 IEEE Workshop On Signal Processing Systems. |
| DOI: | 10.1109/sips.2010.5624879 |
| Popis: | This paper presents a two-iteration concatenated Bose-Chaudhuri-Hocquenghem (BCH) code and its high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. A low-complexity syndrome computation architecture and a high-speed dual-processing pipelined simplified inversonless Berlekamp-Massey (Dual-pSiBM) key equation solver architecture were applied to the proposed concatenated BCH decoder with an aim of implementing a high-speed low-complexity decoder architecture. The proposed two-iteration concatenated BCH code structure with block interleaving methods allows the decoder to achieve 8.91dB of net coding gain performance at 10−15 decoder output bit error rate to compensate for serious transmission quality degradation. Thus, it has potential applications in next generation forward error correction schemes for 100 Gb/s optical communications. |
| Databáze: | OpenAIRE |
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