| Autor: |
Tsung-Yi Chou, Wen-Hua Chang, Tsun-Yuan Fan |
| Rok vydání: |
2015 |
| Předmět: |
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| Zdroj: |
A-SSCC |
| DOI: |
10.1109/asscc.2015.7387467 |
| Popis: |
The presented IEEE802.3an 10GBASE-T transmitter utilized a current-steering DAC and low voltage line driver to achieve the low power requirement. A self-regulated amplifier is used to enhance the operating bandwidth without common mode feedback stability limitation. By using a non-cascode current driver, the center-tap voltage can be lowered to 1. 6 V so that power consumption can be reduced dramatically. The design achieves TX SFDR > 60dB with 2Vppd swing across 400 MHz band and 150mW power consumption. The transmitter is implemented in a 28nm CMOS process with 1.8V/ 1V power domain and occupies an area of 0.11 mm2. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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