8x8 SFQ based Multiplier design using Verilog in Cadence
| Autor: | Ravi Hosamani, Vishwas Patil, Rakesh H M, Manu T.M, Chetan Saraf, Praveen Kumar Y G |
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| Rok vydání: | 2021 |
| Zdroj: | 2021 IEEE International Conference on Mobile Networks and Wireless Communications (ICMNWC). |
| DOI: | 10.1109/icmnwc52512.2021.9688467 |
| Databáze: | OpenAIRE |
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