Wafer stacking: key technology for 3D integration

Autor:	C. Lagahe-Blanchard, B. Aspar
Rok vydání:	2009
Předmět:	Materials science business.industry Stacking Electrical engineering Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY Direct bonding Back end of line Reliability (semiconductor) CMOS Hardware_INTEGRATEDCIRCUITS Optoelectronics Integrated circuit packaging business Metallic bonding
Zdroj:	2009 IEEE International SOI Conference.
DOI:	10.1109/soi.2009.5318779
Popis:	Wafer stacking technologies are today available for different 3D integration schemes. These are compatible with back end of line CMOS processes and packaging. Smart Stacking technology and Copper to Copper direct bonding processes were described as key technologies to realize dielectric or metallic bonding at room temperature and without applied pressure and/or additional glue layer. This results in a low stress stacked structure enabling high yield post process.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7f33ca5a9a8047c3a2c12cb7edf3cab2 https://doi.org/10.1109/soi.2009.5318779 Zobrazit plný text záznamu