Methodology for Hardware testing of an Application Specific Integrated Circuit (ASIC)
| Autor: | null Navneet KaurBrar, null Manu Bansal, null Alpana Agarwal |
|---|---|
| Rok vydání: | 2022 |
| Předmět: | |
| Zdroj: | Journal of Pharmaceutical Negative Results. :2012-2016 |
| ISSN: | 2229-7723 0976-9234 |
| DOI: | 10.47750/pnr.2022.13.s06.262 |
| Popis: | The paper demonstrates an efficient process flow for the Hardware Testing of an ASIC (Application Specific Integrated Circuit). The procedure is implied on Comparator, ADC (Analog-to-Digital) and Present Cipher Crypto ASIC. This involves the testing functionality of an Analog, Digital and Mixed Signal design ASIC. The results obtained during functional testing are verified through simulations on Cadence, in case of comparator and ADC ASIC, and vivado in case of Crypto ASIC. The method gives high accuracy and requires less power even at high frequency. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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