CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications
| Autor: | Ronald J. Pieper, Israel Mejia, Bruce E. Gnade, W. Wondmagegn, Manuel Quevedo-Lopez, H. J. Stiegler, A. L. Salas-Villasenor |
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| Rok vydání: | 2016 |
| Předmět: |
Materials science
Topology (electrical circuits) Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 01 natural sciences law.invention Pentacene chemistry.chemical_compound law 0103 physical sciences Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Electronic circuit 010302 applied physics business.industry Transistor 021001 nanoscience & nanotechnology Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials chemistry CMOS Thin-film transistor Operational amplifier Optoelectronics Inverter 0210 nano-technology business |
| Zdroj: | Microelectronic Engineering. 157:64-70 |
| ISSN: | 0167-9317 |
| Popis: | Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9dB and 29.7dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor. Display Omitted |
| Databáze: | OpenAIRE |
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