STS-768 multiplexer with full-rate output data retimer in InP HBT
| Autor: | Xin Xu, Emilio A. Sovero, K. Witt, A. Hendarman |
|---|---|
| Rok vydání: | 2003 |
| Předmět: |
Engineering
business.industry Heterojunction bipolar transistor Circuit design Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Integrated circuit design Multiplexer Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Multiplication Electrical and Electronic Engineering Transceiver business Jitter |
| Zdroj: | IEEE Journal of Solid-State Circuits. 38:1497-1503 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/jssc.2003.815919 |
| Popis: | A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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