Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop

Autor:	Matthew R. Guthaus, Riadul Islam
Rok vydání:	2015
Předmět:	Physics Synchronous circuit CMOS Clock signal Clock domain crossing Electronic engineering Clock gating Digital clock manager Electrical and Electronic Engineering Clock skew CPU multiplier
Zdroj:	IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1156-1164
ISSN:	1558-0806 1549-8328
DOI:	10.1109/tcsi.2015.2402938
Popis:	We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7ebf6aa38664920497f82ddc311191c1 https://doi.org/10.1109/tcsi.2015.2402938 Zobrazit plný text záznamu