Autor: |
S. Sumi, K. Murano, Tsuda Toshitaka, M. Shimada, H. Kikuchi, Shigeyuki Unagami, Y. Miwa |
Rok vydání: |
2005 |
Předmět: |
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Zdroj: |
ICASSP |
DOI: |
10.1109/icassp.1983.1172149 |
Popis: |
This paper describes a newly developed CMOS LSI DSP and its application to a 32 Kbps ADPCM CODEC and a 4,800 bps data MODEM. The paper first analizes the required memory capacities of ROM and RAM as a function of arithmatic operation capability of DSP. Based on the results, the LSI DSP is developed, which has a proper amount of memory capacities. It has a multiplier which operates at a rate of 1.4 M operations/s. It is also equipped with a versatile I/O interface circuit which is suitable for multi-processors configuration of a system. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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