0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file
| Autor: | F. Sano, Hiroshi Momose, Takayasu Sakurai, K. Matsuda, Yohji Watanabe, Tetsu Nagamatsu, Y. Niitsu, Katsuhiro Seta, A. Chiba, Hiroyuki Miyakawa, Hiroyuki Hara |
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| Rok vydání: | 1992 |
| Předmět: |
Standard cell
Adder Hardware_MEMORYSTRUCTURES CPU cache business.industry Sense amplifier Computer science Register file Hardware_PERFORMANCEANDRELIABILITY BiCMOS Threshold voltage law.invention CMOS Application-specific integrated circuit law Embedded system Logic gate Hardware_INTEGRATEDCIRCUITS Operational amplifier Inverter Electrical and Electronic Engineering business Low voltage Computer hardware Electronic circuit |
| Zdroj: | IEEE Journal of Solid-State Circuits. 27:1579-1584 |
| ISSN: | 0018-9200 |
| DOI: | 10.1109/4.165339 |
| Popis: | BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5- mu m BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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