Autor: |
Yu Qianmin, Zhao Zicai, Zou Xiaowei, Waisum Wong, Cheng Changhong, Li Zan, Sun Lijie, Yu Yong |
Rok vydání: |
2018 |
Předmět: |
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Zdroj: |
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). |
Popis: |
Double Patterning (DP) is imperative process for FinFET, and Metal-Oxide-Metal (MoM) capacitors are crucial passive devices in mixed-signal/analog integrated circuits, the process variation of DP is increased by Metal space, width and dielectrics constant which will be reflected by MoM corner variation. Conventionally, only skew capacitance or resistance to create best and worst case which not including metal cancellation will lead to larger deviation to silicon. A methodology to create best and worst case of MoM considering metal cancellation is proposed for narrowing that gap in this paper. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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