Advanced integration technology for a highly scalable SOI DRAM with SOC (Silicon-On-Capacitors)
| Autor: | Byoung Hun Lee, Gi-ho Cha, Kye-hee Yeom, Joon-hee Lee, Woo-Tag Kang, Yun-Gi Kim, Kyu-Charn Park, Sang-Cheol Lee, Chang-Gyu Hwang, Tae-Earn Shim, Duck-Hyung Lee, Sunil Yu, Sang-In Lee, Il-Kwon Kim |
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| Rok vydání: | 2002 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Materials science business.industry Transistor Electrical engineering Silicon on insulator Hardware_PERFORMANCEANDRELIABILITY law.invention Capacitor Hardware_GENERAL law Chemical-mechanical planarization Shallow trench isolation Hardware_INTEGRATEDCIRCUITS Optoelectronics business Lithography Dram Floating body effect |
| Zdroj: | International Electron Devices Meeting. Technical Digest. |
| DOI: | 10.1109/iedm.1996.554056 |
| Popis: | A fully planarized 16 Mb SOI DRAM has been successfully fabricated featuring pattern-bonded SOI (PBSOI), CMP processes, STI (Shallow Trench Isolation) and the silicon-on-capacitor (SOC) structure with 0.3 um technology using i-line lithography. The floating body effects of cell and peripheral SOI transistors are suppressed by the LIF (Local Implantation post Field oxidation) and halo implantation. The fully planarized process with SOC structure is established for multi-gigabit DRAM and embedded memory devices. |
| Databáze: | OpenAIRE |
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