A high performance dynamic logic with nMOS based resistive keeper circuit
| Autor: | Voicu Groza, Satyendra N. Biswas, Abdullah Al Mamun, Riazul Islam, Sunil R. Das, Kazi Fatima Sharif, Mansour H. Assaf, Md. Shah Miran |
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| Rok vydání: | 2017 |
| Předmět: |
Very-large-scale integration
Engineering Resistive touchscreen business.industry Transistor Logic family Hardware_PERFORMANCEANDRELIABILITY Leakage power law.invention law Domino logic Hardware_INTEGRATEDCIRCUITS Electronic engineering business NMOS logic Dynamic logic (digital electronics) Hardware_LOGICDESIGN |
| Zdroj: | 2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE). |
| DOI: | 10.1109/iscaie.2017.8074950 |
| Popis: | Dynamic logic is highly in demand for designing low power VLSI circuits. It need less number of transistor though but the performance of the dynamic logic is not so promising due to prolonged contention time and higher leakage power. Present research proposes a new nMOS based resistive circuit in order to reduce the contention time for minimum leakage power. Simulation results using LTspice tools demonstrate that the proposed model significantly reduces the contention time as well as the leakage power. |
| Databáze: | OpenAIRE |
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