vfTLP-VTH: A new method for quantifying the effectiveness of ESD protection for the CDM classification test
| Autor: | David F. Ellis, Jean-Jacques Hajjar, Yuanzhong Zhou, Andrew H. Olney, Juin J. Liou |
|---|---|
| Rok vydání: | 2013 |
| Předmět: |
Engineering
business.industry Hardware_PERFORMANCEANDRELIABILITY Condensed Matter Physics Atomic and Molecular Physics and Optics Surfaces Coatings and Films Electronic Optical and Magnetic Materials Reliability engineering Threshold voltage Saturation current Robustness (computer science) Hardware_INTEGRATEDCIRCUITS Electronic engineering Inverter Electrical and Electronic Engineering Safety Risk Reliability and Quality business Device failure Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | Microelectronics Reliability. 53:196-204 |
| ISSN: | 0026-2714 |
| Popis: | A new methodology for quantifying the effectiveness of CDM protection circuits and CDM robustness of I/O circuits is presented in this paper. This method, referred to as the vfTLP-V TH , consists of applying vfTLP stresses to test structures composed of the ESD protection and the device or circuit to be protected: a MOS device or a MOS inverter. The protected structures are used as monitors and shifts in their characteristics, such as MOS threshold voltage V TH and saturation current I DD , are used to probe device failure criteria. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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