| Popis: |
The ESD-ability effect of parasitic p-type Schottky diodes on the high-voltage pLDMOS is evaluated in this paper. By using the TLP testing machine, it can be used to analyze the component of snapback I-V measurement values such as component trigger voltage (V t1 ), holding voltage (V h ), and secondary breakdown current (I t2 ) data. Finally, it can be found that this parasitic Schottky device structure can be regarded as adding a reverse Schottky diode in series at the drain-end of the reference device. In this way, the on-resistance of the component increases, and the trigger voltage (V t1 ) tends to be increased too. It is also found that as the area ratio (>85%) of the reverse Schottky diode of the drain-end increases, the current density at the drain terminal becomes more dispersed. Then, the immunity of components to ESD is also significantly improved. |
