10 bit 200 MS∕s CMOS D∕A converter employing high-speed limiter
| Autor: | Min-hyung Cho, Seung-Chul Lee, Hyun-Kyu Yoo |
|---|---|
| Rok vydání: | 2002 |
| Předmět: |
Engineering
Spurious-free dynamic range business.industry Transistor Electrical engineering Feedthrough Hardware_PERFORMANCEANDRELIABILITY Voltage regulator Integrated circuit design law.invention PMOS logic CMOS law Hardware_INTEGRATEDCIRCUITS Limiter Electronic engineering Electrical and Electronic Engineering business |
| Zdroj: | Electronics Letters. 38:1407 |
| ISSN: | 0013-5194 |
| DOI: | 10.1049/el:20021013 |
| Popis: | A 10 bit 200 MS/s CMOS current-steering digital-to-analogue converter (DAC) employing a new voltage limiter to reduce the feedthrough of the control signals is presented. For high-speed operation of the limiter, a design technique based on the parasitic capacitor of a PMOS transistor is proposed. At 200 MS/s, a spurious-free dynamic range of 65 dBc for a 40 MHz output signal has been achieved from the proposed DAC. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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