A 1.5-V 3.2Gb/s/pin Graphic DDR4 SDRAM with Dual-Clock System, 4 Phase Input Strobing and Low Jitter Fully Analog DLL

Autor:	Joo-Hwan Cho, Ki-Won Lee, Byoung-Jin Choi, Geun-Il Lee, Kwang-Jin Na, Ho-Don Jung, Woo-Young Lee, Ki-Chon Park, Yong-Suk Joo, Jae-Hoon Cha, Se-Jun Kim, Young-Jung Choi, Patrik B. Moran, Jin-Hong Ahn, Joong-Sik Ki
Rok vydání:	2006
Zdroj:	2006 IEEE Asian Solid-State Circuits Conference.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::7d81de98e8a213130b29938d1d1d4d13 https://doi.org/10.1109/asscc.2006.357846 Zobrazit plný text záznamu