A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
| Autor: | Chang-Yong Lee, Seung-Jun Bae, Jeong-Woo Lee, Seung-Hoon Oh, Yong-Hun Kim, Young-Soo Sohn, Gyo-Young Jin, Gong-Heum Han, Dong-seok Kang, Young-Hun Seo, Gun-hee Cho, Seung-Hyun Cho, Sam-Young Bang, Seong-Jin Jang, Youn-sik Park, Yong-Jun Kim, Kwang-Il Park, Jung-Hwan Choi, Seouk-Kyu Choi, Kyung-Bae Park, Sung-Geun Do, Young-Ju Kim, Keon-woo Park, Ji-Hak Yu, Jae-Sung Kim, Su-Yeon Doo, Jae-Koo Park, Chan-Yong Lee, Chang-Ho Shin, Hye-Jung Kwon, Byung-Cheol Kim, Hyuk-Jun Kwon, Sang-Sun Kim, Min-Su Ahn, Hyun-Soo Park, Chul-Hee Jeon, Lee Yong-Jae, Ki-Hun Yu, Sang-Yong Lee |
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| Rok vydání: | 2019 |
| Předmět: |
Random access memory
business.industry Computer science 020208 electrical & electronic engineering Bandwidth (signal processing) 02 engineering and technology Phase-locked loop 0202 electrical engineering electronic engineering information engineering Signal integrity Electrical and Electronic Engineering business Electrical impedance Computer hardware Dram |
| Zdroj: | IEEE Journal of Solid-State Circuits. 54:197-209 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE), a reference impedance (ZQ)-coded transmitter, and a phase-locked loop (PLL)-less clocking to overcome I/O speed limitation by the DRAM process. Furthermore, this paper optimizes clock- and power-domain crossings and adopts split-die architecture to improve signal integrity (SI). This GDDR6 operates 16 Gb/s/pin with 1.15 V and achieves 18 Gb/s/pin with 1.35 V in the DRAM process. |
| Databáze: | OpenAIRE |
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